Texas Instruments Documents.

The following was published in TILines in the 1980s, and is a combination of data from various manuals and my own inputs. -[Colin Hinson]

On reading various letters in this and other magazines it is apparent that there is much confusion about GROMs and the way they are used in the 99/4a. In order to remove as much of this confusion as possible, there follows a description of the GROMs themselves and the way they are used in the 99/4a.

GENERAL DESCRIPTION.

A GROM is a P-channel read only memory containing 6144 8-bit bytes. It has an on chip auto-incrementing address counter which selects one of the 6144 memory bytes. The address register is loaded by writing the 2 bytes of the address MSB first.

FUNCTIONAL DESCRIPTION

CPU INTERFACE
The GROM interfaces to the CPU through the 8 bit parallel data bus and various memory control lines. These control lines consist of the Chip Enable (CE), READY, and two mode control lines (M0 & M1). The GROM also requires a nominal 500kHz clock input (OSC).

GROM PAGING
The GROM has a 16 bit address register of which the lower 13 bits are used to address the 6144 byte ROM matrix. The most significant 3 bit field is used to select one of eight GROM pages. Each GROM has a fixed 3 bit page number which is DETERMINED DURING MANUFACTURE. The GROM compares this number with the address register page select field. If a match occurs, tthen the GROM is the "selected page" or "current page". The GROM data bus is placed into the output mode during a read data operation only if the GROM is the current page. The other GROM functions are not affected by the page select field. The page select field permits up to eight GROMs to be used in parallel. Each GROM is tied to the same chip enable, memory control and data lines as the other GROMs. Since the page select field does not affect the data register or address register operations, all parallel GROMs are synchronised following initialisation. However, since only one GROM is the current page, only one GROM outputs data on the data bus during a read operation. If no GROM is selected (the address register page field does not match the page number of any GROM), then no GROM is placed into the output mode during a read operation. During a read address operation, all GROMs output the address byte. Since all GROMs are synchronised, no data bus conflict occurs.

ADDRESS REGISTER AUTO-INCREMENTATION
The address counter is auto-incremented following a read data, write data, or a pair of consecutive write address operations. When the current address is 8191, the next auto-increment cycle will result in a zero address value. The page select field is NOT affected by this auto-increment.
When the value of the address register lower 13 bit field is greater that 6143, the GROM will continue to fetch data from the 6144 byte array. This condition should be avoided in order to prevent invalid data fetches and transfers.

INITIALISATION
During the console power up sequence, the microprocessor executes "dummy" read data operation. This guarantees that a newly powered up GROM will not respond to the first write address operation as if it were the second write address operation. The microprocessor then initialises the GROM address registers with two valid consecutive write address operations (i.e. it writes two 8 bit bytes).

READY
The GROM ready line is normally low, and is high only when the GROM has an active Chip Enable and has read the contents of the data bus during a write operation, or has placed data on the bus during a read operation. The READY line control is independent of the page select.

ACCESS DELAY
A GROM requires that a second I/O operation should not occur before it has completed the first operation. Consequently, CE must remain high at least 2.5 GROM CLOCK cycles following the trailing edge of the last I/O operation. For a nominal 500kHz OSC input, the minimum required delay for access is therefore 5 microseconds.

I/O OPERATIONS. When the CE becomes active (low), the mode lines determine which one of four GROM I/O operations is to occur as shown below:

M0=0, M1=0 WRITE DATA.
The write data operation was originally included for use in future read/write versions of the GROM, though no such device was ever produced. However various GROM emulators make use of this feature, as it enables data from disc to be stored in a RAM which is accessed via external TTL counters, thus emulating a GROM.

M0=0, M1=1 READ DATA
The read data operation transfers the data byte in the data register to the CPU if the GROM is the current page. The address register is then auto- incremented. The addressed ROM byte is fetched and placed in the GROM data register.

M0=1, M1=0 WRITE ADDRESS -
The write address operation transfers the data byte on the GROM data I/O bus to the least significant byte (LSB) of the GROM address register. The old address register LSB is transferred to the address register MSB. Two consecutive write address operations cause the addressed ROM byte to be fetched and placed into the GROM data register; the address register is then auto-incremented. A write address operation immediately following a read data, read address or write data operation does not result in a data fetch and address auto-incrementation.

M0=1, M1=1 READ ADDRESS
The read address operation transfers the MSB of the address register to the CPU if the GROM is the current page. The address register LSB is automatically transferred to the MSB.

It should be noted that the M0 line controls whether the data or address register is to be affected and the M1 line controls whether the operation is an input or output cycle.

The 99/4a has three internal GROMS (pages 0, 1, & 2), giving the capability of 5 more external GROMs to be added in a module via the GROM port (though with suitable external hardware, a module library of up to 16 modules can be added - the console software exists to drive this, though the hardware does not. The software gives such instructions as "INSERT MODULE" and "REVIEW MODULE LIBRARY" which you may have seen when the console crashes).

GROM CLOCK
The clock signals for the GROMs are derived from the VDP. The clock cycle time is 2.24 microseconds. A 1k pull up resistor to +5v is used to give a full 0v to 5v swing as is required by P-channel devices.

MODE CONTROL
The CPU signal DBIN (Data Bus In) is connected to M1 to control the read/write operations, and the address line A14 goes to M0 to control the data/address operations. Thus a read operation is performed when DBIN is high and a write operation when DBIN is low.

GROM SELECT
The GROM select line is generated by decoding the appropriate addresses via two 3 line to 8 line decoders, the line going low to select the GROMs.

GROM READY
The GROM READY signal is connected to the CPU ready line via an inverter and some gates. The signal is only gated to the CPU when the GROM SELECT line is active (low).

ADDRESS	TYPE OF INSTRUCTION
>9800	READ GROM DATA
>9802	READ GROM ADDRESS
>9C00	WRITE GROM DATA
>9C02	WRITE GROM ADDRESS

RESET	1	2	GROUND
D7	3	4	CRU CLOCK-
D6	5	6	CRU IN
D5	7	8	A15/CRU OUT
D4	9	10	A13
D3	11	12	A12
D2	13	14	A11
D1	15	16	A10
D0	17	18	A9
+5 V	19	20	A8
GROM SELECT	21	22	A7
A14	23	24	A3
DBIN	25	26	A6
GROM CLOCK	27	28	A5
-5 V	29	30	A4
GROM READY	31	32	WE-
GROM VSS	33	34	ROM G-
GROUND	35	36	GROUND

The above diagram is drawn looking into the Grom Port from the front of the Console, the top of the console is to the right. The Power supply rails are -5v, +5v, -0.7v (GROM VSS), and Ground.

RESET - Yes this is an output signal, and goes either directly to -5V or through a 100 ohm resistor to -5v on all modules.

The bi-directional signals are the 8 data bits D0 to D7 All the remaining signals are inputs to the modules. Notice that the arrangement of the signals allows modules which contain only GROMS to use a single sided printed circuit board, as all the GROM signals are on the bottom. Modules with ROMs require a double sided PCB.

D7	1	16	VSS
D6	2	15	GROM READY
D5	3	14	-5V
D4	4	13	GROM CLOCK
D3	5	12	M1
D2	6	11	M0
D1	7	10	GROM SELECT
D0	8	9	+5v

GRAPHIC READ ONLY MEMORIES (GROMs)

GENERAL DESCRIPTION.

FUNCTIONAL DESCRIPTION